In some integrated circuit stacked die packaging, such as 3D or TSS (Through Silicon Stacking) integrated circuit packaging, two or more dice (chips) are stacked on top of each other. For example, a first tier die may be bonded to a package substrate, and a second tier die may be bonded on top of the first tier die. Conductive bumps on the bottom of the second tier die are electrically coupled to conductive bumps on the top of the first tier die. This electrical coupling may be realized by soldering. The first tier and second tier dice may be positioned relative to each other so that their active sides are facing each other. As another example, the active side of the second tier die may be on top, where through-silicon vias provide electrical connection between the active side of the second tier die and the bottom side having the conductive bumps. Additional dice may be stacked on top of the second tier die.
When bonding one die to another die, as one die first comes into electrical contact with the other die, there may be an electrostatic discharge (ESD), which may damage the integrated circuits disposed therein. Although in many applications ESD protection may be provided at the circuit level, in the case of TSS packaged integrated circuits, it is desirable to reduce or eliminate the amount of circuit level ESD protection between the different integrated circuit tiers so as not to introduce parasitic capacitances. Also, current methods to reduce the likelihood of ESD events, such as grounding a die or ionizing the surrounding air, may not be as effective in TSS packaging technology in comparison to single die integrated circuit packaging. Accordingly, it is desirable to reduce the risk of ESD damage when manufacturing TSS packaged integrated circuits without introducing additional ESD circuits.